-------------------------------------------------------------------------------
--
-- Title       : No Title
-- Design      : test3
-- Author      : aldec
-- Company     : Microsoft
--
-------------------------------------------------------------------------------
--
-- File        : c:\Users\vincenti\Desktop\testworkspace\wkspace\test3\compile\test.vhd
-- Generated   : 02/10/15 16:15:32
-- From        : c:\Users\vincenti\Desktop\testworkspace\wkspace\test3\src\test.asf
-- By          : FSM2VHDL ver. 5.0.7.2
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity test is 
	port (
		a: in STD_LOGIC;
		CLK: in STD_LOGIC;
		clk_en: in STD_LOGIC;
		reset: in STD_LOGIC;
		z: out STD_LOGIC);
end test;

architecture test_arch of test is

-- diagram signals declarations
signal delay_counter_Sreg0: INTEGER range 0 to 3;

-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (
    S4_S5, S4_D1_DS1, S1, S3, S2
);
-- attribute ENUM_ENCODING of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding

signal Sreg0: Sreg0_type;

begin


----------------------------------------------------------------------
-- Machine: Sreg0
----------------------------------------------------------------------
Sreg0_machine: process (CLK)
begin
	if rising_edge(CLK) then
		if reset='1' then
			Sreg0 <= S1;
			-- Set default values for outputs, signals and variables
			-- ...
			z <= '1';
		else
			if clk_en = '1' then
				-- Set default values for outputs, signals and variables
				-- ...
				case Sreg0 is
					when S1 =>
						z <= '1';
						if a = '1' then
							Sreg0 <= S2;
						end if;
					when S3 =>
						z <= '0';
						Sreg0 <= S4_S5;
					when S2 =>
						z <= '1';
						if a = '1' then
							Sreg0 <= S3;
						end if;
					when S4_S5 =>
						Sreg0 <= S4_D1_DS1;
						delay_counter_Sreg0 <= 3 - 1;
					when S4_D1_DS1 =>
						if (delay_counter_Sreg0 = 0) and (a = '1') then
							Sreg0 <= S1;
						else
							Sreg0 <= S4_D1_DS1;
							if delay_counter_Sreg0 /= 0 then delay_counter_Sreg0 <= delay_counter_Sreg0 - 1;
							end if;
						end if;
--vhdl_cover_off
					when others =>
						null;
--vhdl_cover_on
				end case;
			end if;
		end if;
	end if;
end process;

end test_arch;
